Erick and I were saying we'd like to have a basic prototype bootstrapping VM working by the end of the summer. We'd like to discuss the technical choices involved when we return from here.
I would personally like to get the IR framework in place before working on code gen. I see the x86 code generation as being the last phase of the IR translation process. I was thinking we could do a basic job at x86 code gen for now. Translating from the AST to SSA HIR, and then to a lower level IR will make the code gen quite a bit easier, and we can integrate it into the IR framework.
I actually spoke to someone who worked on the Sun JVM, and is now working on the Azul JVM. He told me that this is basically how those systems implemented this. Their VM converts to SSA early on, optimizes, eventually translates the instructions down to x86 code, and runs register coloring on the SSA temps to do both register and stack slot allocation at once at the end, before doing basic block straightening and emitting the actual code stream.
- Maxime
We need to start implementing the x86 code generator and in-memory assembler. Once we have that we can start experimenting with dynamic code generation and start work on the Tachyon back-end. We can use the code I wrote for the Gambit x86 back-end as a starting point. It supports code generation for 32 and 64 bit architectures and most of the instructions and addressing modes we need are implemented. So this work will be in large part a translation effort from Scheme to JS. The in-memory assembler is about 800 lines of Scheme. The x86 code generator is about 1400 lines of Scheme.
Who is interested in working on this?
Marc
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